The present invention relates to an electrically programmable, erasable nonvolatile semiconductor memory device having a trap layer in a gate insulation film formed between a channel region and a gate electrode of each memory cell transistor, and a programming or erasing method for such a semiconductor memory device.
In a conventional nonvolatile memory having a trap layer, electric charge (electrons and holes) is trapped by injection of the charge in a discrete trap layer (a SiN film or a transition region at the interface of a SiN film/a top SiO2 film) existing inside an insulating film (SiO2) formed between a channel region and a gate electrode of a memory cell. Data “0” or data “1” is determined with respect to the threshold voltage of the memory cell, to thereby store information.
Hereinafter, description will be made regarding injection of electrons as programming (write) while injection of holes as erasing, and also regarding injected charge and surrounding charge in programming (write) operation as electrons and holes respectively.
FIG. 19 is a schematic cross-sectional view of a nonvolatile memory having a trap layer, with the x-axis representing the channel direction. Using FIG. 19, the configuration and operation of the conventional nonvolatile memory having a trap layer will be described.
Referring to FIG. 19, the nonvolatile memory includes: a semiconductor substrate 1801 made of p-type silicon; a p-type channel region 1802 located above the semiconductor substrate 1801; a first impurity region 1803 made of n-type semiconductor located above the semiconductor substrate 1801 on one side of the channel region 1802; a second impurity region 1804 made of n-type semiconductor located above the semiconductor substrate 1801 on the other side of the channel region 1802; a bottom insulating film 1807 made of a silicon oxide film placed above the semiconductor substrate 1801; a trap layer made of a silicon nitride/oxide film placed on the bottom insulating film 1807; a top insulating film 1805 made of a silicon oxide film placed on the trap layer 1806; and a gate electrode 1808 made of n-type polysilicon placed on the top insulating film 1805.
In programming, about 9 V is applied to the gate electrode 1808, about 5 V to the first impurity region 1803, about 1 V to the second impurity region 1804 and 0 V to the semiconductor substrate 1801. With this voltage application, part of electrons moving from the second impurity region 1804 to the first impurity region 1803 is made hot with a high electric field in the neighborhood of the first impurity region 1803, and thus locally injected into the trap layer 1806. This turns the memory cell threshold voltage to a high state.
In erasing, about −3 V is applied to the gate electrode 1808, about 5 V to the first impurity region 1803, and 0 V to the semiconductor substrate 1801, while the second impurity region 1804 is put in a floating state. With this voltage application, part of holes generated due to inter-band tunneling inside the first impurity region 1803 is made hot with a high electric field in the neighborhood of the first impurity region 1803, and thus locally injected into the trap layer 1806. Thus turns the memory cell threshold voltage to a low state.
In reading, about 4 V is applied to the gate electrode 1808, 0 V to the first impurity region 1803, about 1.5 V to the second impurity region 1804, and 0 V to the semiconductor substrate 1801. With this voltage application, data “0” or “1” is obtained depending on existence/absence of charge in the trap layer 1806.
Next, referring to FIGS. 20A through 20E, the behavior of trapped charge in a non-biased state after programming in the conventional nonvolatile memory having a trap layer will be described.
FIGS. 20A and 20B show distributions of the memory cell threshold voltage, where the x-axis represents the memory cell threshold voltage and the y-axis represents the number of memory cells targeted for programming. FIGS. 20C through 20E show the probability density distributions in the neighborhood of the first impurity region 1803 in FIG. 19, where the x-axis represents the distance in the direction of arrow x in FIG. 19 and the y-axis represents the charge density.
FIG. 20A shows a distribution 1901 of the memory cell threshold voltage observed immediately after programming. FIG. 20B shows a distribution 1902 of the memory cell threshold voltage in the last period of life. The reference numeral 1903 denotes a verify level. FIG. 20C shows a probability density distribution 1911 of electrons injected under programming and a probability density distribution 1912 of holes injected under erasing preceding the programming. FIG. 20D shows a probability density distribution 1921 of electrons after binding with holes, and a probability density distribution 1922 of holes after binding with electrons. FIG. 20E shows a probability density distribution 1931 of electrons in the last period of life.
In the state in which two types of charge are locally trapped as described above, in the distribution 1901 of the memory cell threshold voltage observed immediately after programming, electrons and holes exhibit different probability density distributions 1911 and 1912 from each other as shown in FIG. 20C. At overlap portions of the probability density distributions 1911 and 1921 of electrons and of holes, electrons and holes are bound together instantaneously, to exhibit the probability density distribution 1921 of electrons and the probability density distribution 1922 of holes as shown in FIG. 20D. The binding between electrons and holes advances thereafter due to lateral charge diffusion, causing a change in memory cell threshold voltage.
In the distribution 1902 of the memory cell threshold voltage in the last period of life, since the total number of electrons is greater than that of holes in the programming state, holes disappear, and thus only the probability density distribution 1931 of electrons exists as shown in FIG. 20E. Thus, by reducing the total number of holes after programming, the data retention characteristic of memory cells can be improved.
According to U.S. Pat. No. 5,365,486, a memory cell of which the threshold voltage becomes too low due to a disturb to satisfy the verify level is programmed again, so that the verify level can be satisfied, and thus the memory cell threshold voltage can be suppressed from changing.
In the conventional nonvolatile memory having a trap layer, when charge is locally injected into the trap layer, the trapped charge diffuses in the lateral direction in a non-biased state and is bound with surrounding charge, causing a change in memory cell threshold voltage. The data retention characteristic deteriorates with this change in memory cell threshold voltage, and this causes lowering of the access speed and erroneous read of data in the market.
The data retention characteristic depends on the number of times of programming or erasing: as the number of times of programming or erasing is greater, the data retention characteristic deteriorates more greatly, blocking improvement in the guaranteed number of times of programming or erasing for products.